The present invention generally relates to a method for fabricating a compound semiconductor device, and more particularly relates to a method for fabricating a field effect transistor (FET) for use in a compound semiconductor integrated circuit (IC) operating on microwave and millimeter wave bands.
In a conventional compound semiconductor device, such as an FET, a recessed structure is commonly used to improve the uniformity of a threshold voltage (hereinafter, referred to as "Vth") within a wafer plane and increase a breakdown voltage between gate and source and between gate and drain. In the recessed structure, part of an ohmic contact layer, which is located over a Schottky layer and in which a gate electrode should be formed (hereinafter, referred to as a "cap layers"), is selectively etched to have an opening larger in width than an etching mask.
FIGS. 6A through 6C are cross-sectional views illustrating conventional process steps for fabricating a compound semiconductor FET 400 (hereinafter, simply referred to as a "compound FET" for the sake of simplicity). Although only one compound FET is shown in FIGS. 6A through 6C, typically a plurality of compound FETs 400 are fabricated in a single wafer.
First, as shown in FIG. 6A, an undoped GaAs buffer layer 12 (thickness: about 300 nm); an undoped InGaAs channel layer 13 (thickness: about 15 nm); an n-type AlGaAs electron supply layer 14 (thickness: about 10 nm) doped with Si at about 1.times.10.sup.18 cm.sup.-3 ; an undoped AlGaAs Schottky layer 15 (thickness: about 20 nm); and an n-type GaAs cap layer 16 (thickness: about 100 nm) doped with Si at about 3.times.10.sup.18 cm.sup.-3 are stacked in this order on a semi-insulating GaAs substrate 11. Then, source and drain electrodes 19 and 20 are formed to be spaced apart from each other on the cap layer 16 by stacking AuGe, Ni and Au layers (AuGe/Ni/Au) in this order thereon.
Next, as shown in FIG. 6B, a patterned resist film 28 is formed over the cap layer 16. Then, using this resist film 28 as an etching mask and a mixed gas of BCl.sub.3 and SF.sub.6, the cap layer 16 is dry-etched isotropically and selectively with respect to the Schottky layer 15, thereby forming a recessed portion 22 over the Schottky layer 15 to be larger in width than the opening of the resist film 28.
Next, an Al layer is deposited over the resist film 28. As shown in FIG. 6C, a gate electrode 23 made of the Al layer is formed on the bottom of the recessed portion 22 by a lift-off technique using the resist film 28.
According to this conventional method, only the cap layer 16 is selectively dry-etched isotropically using the mixed gas of BCl.sub.3 and SF.sub.6. Thus, the recessed portion 22 is formed to a uniform depth within the substrate (or wafer) 11, and therefore the threshold voltage Vth is highly uniform within the wafer plane. Also, since the recessed portion 22 is formed to be larger in width than the opening of the resist film 28, the gate electrode 23 is much less likely to come into contact with the cap layer 16. As a result, an FET with an increased breakdown voltage between gate and source or drain can be obtained.
According to this method, however, the distance between one edge of the opening of the resist film 28 and that of the recessed portion 22 (hereinafter, referred to as a "side-etch distance", which is identified by s in FIG. 6B) is equal to or larger than the thickness (which is identified by d in FIG. 6B) of the cap layer 16. This is because the recessed portion 22 is formed only by isotropic selective dry etching. Thus, the side-etch distance s cannot be smaller than the thickness d of the cap layer 16.
The gate-source and gate-drain breakdown voltages increase with the increase in side-etch distance. However, the gate-source and gate-drain resistance also increases correspondingly, and the transconductance decreases as a result. That is to say, a tradeoff is inevitable between gate breakdown voltage and transconductance in the performance of a semiconductor device of this type.
Accordingly, to regulate a gate breakdown voltage and transconductance depending on the required device performance and/or specific device structure, it is desirable to develop a method for forming a recessed structure, by which the side-etch distance can be controlled independently of the thickness of the cap layer 16.